The present invention generally relates to Schmitt trigger circuits, and more particularly to a Schmitt trigger circuit having a satisfactory hysteresis characteristic.
A Schmitt trigger circuit has a hysteresis characteristic in which a threshold voltage V.sub.T.sup.+ is high with respect to a rise of an input voltage and a threshold voltage V.sub.T.sup.- is lower than the threshold voltage V.sub.T.sup.+ with respect to a fall of the input voltage. Due to this hysteresis characteristic, a noise margin of the Schmitt trigger circuit is high and the Schmitt trigger circuit can prevent oscillation in a vicinity of a fixed threshold voltage. Hence, the Schmitt trigger circuit is suited for use in a long transmission path since noise easily mixes into the long transmission path and a signal waveform is often distorted in the long transmission path.
In the Schmitt trigger circuit, it is desirable to suppress an increase in an input current I.sub.IL which is generated when the input voltage falls from the high level to the low level, the reason being that a load on a driver which drives the Schmitt trigger circuit becomes large when the input current I.sub.IL is large. For example, the Schmitt trigger circuit is used in each bus line of a personal computer. Accordingly, when there are ten bus lines, for example, a total of the input currents I.sub.IL of ten Schmitt trigger circuits becomes large when the input current I.sub.IL increases, thereby making the load on the driver considerably large as a whole.
FIG. 1 shows an example of a conventional Schmitt trigger circuit. This Schmitt trigger circuit has an input stage PNP transistor T1, a Schottky barrier clamped NPN transistor T2 for inversion, a Schottky barrier clamped NPN transistor T3 for setting the hysteresis, a Schottky barrier clamped NPN transistor T4 for controlling the transistor T3, output stage NPN transistors T5 through T*, diodes D1, D2 and Ds1, and resistors R1 through R7 which are connected as shown. The transistors T5, T6 and T8 are Schottky barrier clamped NPN transistors. The diodes D1 and D2 are each constituted by an NPN transistor having a base and a collector thereof short-circuited. The diode Ds1 is a Schottky barrier diode having a cathode connected to an input terminal 1 and an anode connected to a node N1. The node N1 is connected to a base of the transistor T2, an emitter of the transistor T3 and the like. The diode Ds1 is provided for the purpose of extracting a base charge of the transistor T2.
When an input voltage V.sub.IN applied to the input terminal 1 has a low level (for example, 0 V), an emitter voltage of the transistor T1 is only V.sub.BET1 higher than the low-level input voltage V.sub.IN and the transistor T2 turns OFF, where V.sub.BET1 is a base-emitter voltage of the transistor T1. Hence, the transistor T5 turns ON, the transistors T6 and T7 forming a Darlington pair both turn OFF, and the transistor T8 for inverting the output turns ON, thereby resulting in a low-level output voltage V.sub.O being outputted from an output terminal 2. In this state, a current flows from the resistor R2 to the transistor T5 through the base and emitter of the transistor T4.
The transistor T2 turns ON when the emitter voltage of the transistor T1 is V.sub.BED1 +V.sub.BED2 +V.sub.BET2 or higher, where V.sub.BED1 and V.sub.BED2 respectively denote base-emitter voltages of the transistors constituting the diodes D1 and D2 and V.sub.BET2 denotes a base-emitter voltage of the transistor T2. Hence, the input voltage V.sub.IN needs to be (V.sub.BED1 +V.sub.BED2 +V.sub.BET2)-V.sub.BET1 or higher in order to turn ON the transistor T2. In other words, when the input voltage V.sub.IN is (V.sub.BED1 +V.sub.BED2 +V.sub.BET2)-V.sub.BET1 or higher, the transistor T2 turns ON, the transistor T5 turns OFF, the transistors T6 and T7 both turn ON, and the transistor T8 turns OFF, thereby resulting in a high-level output voltage V.sub.O being outputted from the output terminal 2. Thus, (V.sub.BED1 +V.sub.BED2 +V.sub.BET2)-V.sub.BET1 corresponds to a threshold voltage V.sub.T + of the Schmitt trigger circuit when switching the output voltage V.sub.O from the low level to the high level.
In this state, a current flowing through the resistor R2 is supplied to the base of the transistor T3 through the base and collector of the transistor T4, and the transistor T3 turns ON. A collector-emitter voltage (saturation voltage) V.sub.CET3 of the transistor T3 in the ON state is lower than the base-emitter voltage V.sub.BED1 of the diode D1. For this reason, a current flowing through the resistor R1 is supplied to the base of the transistor T2 through the collector and emitter of the transistor T3.
In a process of the input voltage V.sub.IN falling from the high level (for example, 3 V) to the low level, the transistor T2 turns OFF under the condition that the input voltage V.sub.IN is (V.sub.BED2 +V.sub.BET2 +V.sub.CET3)-V.sub.BET1, where V.sub.CET3 denotes a collector-emitter voltage of the transistor T3. This voltage (V.sub.BED2 +V.sub.BET2 +V.sub.CET3)-V.sub.BET1 corresponds to a threshold voltage V.sub.T.sup.- of the Schmitt trigger circuit when switching the output voltage V.sub.O from the high level to the low level. When it is assumed that the base emitter voltages of the transistors T1 and T2 and the diodes D1 and D2 are the same and respectively denoted by V.sub.BE, because V.sub.CET3 is smaller than V.sub.BE =V.sub.BED1, the threshold voltage V.sub.T.sup.- is lower than the threshold voltage V.sub.T.sup.+. Therefore, the relationship between the input voltage V.sub.IN and the output voltage V.sub.O becomes as shown in FIG. 2 which is a hysteresis characteristic.
On the other hand, FIG. 3 shows a Schmitt trigger circuit proposed in a Japanese Published Patent Application No. 58-47093. In FIG. 3, those parts which are essentially the same as those corresponding parts in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted. This proposed Schmitt trigger circuit differs from the conventional Schmitt trigger circuit shown in FIG. 1 in that a multi-emitter PNP transistor T9 is used in the input stage and the diode Ds1 is omitted. A first emitter E1 of the transistor T9 is connected to the resistor R1, while a second emitter E2 of the transistor T9 is connected directly to the base of the transistor T2.
According to the proposed Schmitt trigger circuit shown in FIG. 3, a sum (V.sub.CET3 +V.sub.BET92) of the collector-emitter voltage V.sub.CET3 of the transistor T3 and a voltage V.sub.BET92 across a base and the second emitter E2 of the transistor T9 is higher than a voltage V.sub.BET91 across the base and the first emitter E1 of the transistor T9 in the process of the input voltage V.sub.IN falling from the high level to the low level. Hence, the input current I.sub.IL always flows through the transistor T9 even when the level of theinput voltage V.sub.IN falls and the transistor T9 turns ON, and the input current I.sub.IL is small.
But in the process of the input voltage V.sub.IN falling from the high level to the low level in the conventional Schmitt trigger circuit shown in FIG. 1, a sum (V.sub.CET3 +V.sub.F) of the collector-emitter voltage V.sub.CET3 of the transistor T3 and a forward drop voltage V.sub.F of the diode Ds1 is approximately equal to the base-emitter voltage V.sub.BET1 of the transistor T1. For this reason, at a time immediately before the transistor T5 turns ON and the transistor T3 turns OFF when V.sub.IN =2V.sub.BE -V.sub.F, a current flows from the resistor R1 to not only the base of the transistor T2 through the collector and emitter of the transistor T3 but also to the input terminal 1 through the diode Ds1 although for a short time. In this state, the input current I.sub.IL is a sum of the base current of the transistor T1 and the forward current of the diode Ds1.
When the input voltage V.sub.IN becomes lower than the threshold voltage V.sub.T.sup.-, the transistor T3 turns OFF and the forward current of the diode Ds1 does not flow. In this case, the input current I.sub.IL consists solely of the base current of the transistor T1.
The forward current of the diode Ds1 is a relatively large current, and thus makes the input current I.sub.IL large. This is because, when a current amplification of the transistor T1 is denoted by B1 and a current flowing through the resistor R1 is denoted by Ia, the base current of the transistor T1 is a Ia/B1 while the forward current of the diode Ds1 is not multiplied by 1/B1.
FIG. 4 shows simulation results obtained for the input current I.sub.IL of the conventional Schmitt trigger circuit shown in FIG. 1, where a power source voltage Vcc is set to 5.0 V and the low level and the high level of the input voltage V.sub.IN are respectively set to 0 V and 3 V. It can be seen from FIG. 4 that a peak value of the input current I.sub.IL is approximately -2.2 mA which is considerably large. Hence, there is a problem in that this large input current I.sub.IL results in a large load when viewed from the input side.
On the other hand, in the proposed Schmitt trigger circuit shown in FIG. 3, it is possible to suppress the increase of the input current I.sub.IL in the pulse form in the process of the input voltage V.sub.IN falling from the high level to the low level. But the level at which the base charge of the transistor T2 is extracted, that is, the base voltage of the transistor T2 must be less than or equal to the sum (V.sub.BET2 +V.sub.BED2) of the base-emitter voltages of the transistor T2 and the diode D2. This means that the input voltage V.sub.IN applied to the input terminal 1 must be (V.sub.BET2 +V.sub.BED2)-V.sub.BET92 or less in order to cut off the transistor T2. For this reason, comopared to the input voltage V.sub.IN of the conventional Schmitt trigger circuit shown in FIG. 1 which is (V.sub.BET2 +V.sub.BED2)-V.sub.F, the input voltage V.sub.IN of the proposed Schmitt trigger circuit shown in FIG. 3 is V.sub.BET92 -V.sub.F lower. When it is assumed that the base-emitter voltages of the transistors T2 and T9 and the diode D2 are the same and respectively denoted by V.sub.BE, the input voltage V.sub.IN of the conventional Schmitt trigger circuit is 2V.sub.BE -V.sub.F while the input voltage V.sub.IN of the proposed Schmitt trigger circuit is V.sub.BE and V.sub.BE -V.sub.F lower. As a result, it takes time for the transistor T2 to switch from the ON state to the OFF state in the proposed Schmitt trigger circuit, and there is a problem in that the switching speed is slow.